Applying The WT Protocol

Consider the transitions

P1 reads a into cache

P3 reads a into cache

P1 writes a to 5, and

writes through to main

memory, correcting it

P3 sees WT, invalidates

P2 reads a into cache

P1: I ---> V

PrRd/BusRd

P3: I ---> V

PrRd/BusRd

P1: V ---> V

PrWr/BusWr

P3: V ---> I

BusWr/--

P2: I ---> V

PrRd/BusRd

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