Multi-Level Logic Optimization

• Primary Goal: Reduce number of literals in circuit

  • literal: occurrence (true or comp) of an input or temporary value
  • each literal translates to 2 transistors
  • this reflects CMOS standard cell implementation
  • “technology-independent” measure
    • we assume this goal will be good for FPGAs

• Method: factoring and common subexpressions

  • different kinds of factors
    • cubes & kernels
  • different ways to factor
    • algebraic & boolean
  • cannot try all combinations ? heuristics

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