Multi-level Logic for FPGAs
FPGA Goal: Implement using max-fanin functions (LUTs)
- different from minimizing # of literals
What works well for FPGAs:
- run multi-level logic minimization (minimize # of literals)
- post-process to cover graph with max-fanin functions (LUTs)
- “collapse” collections of small-input functions
- factor large-input functions
Multi-level logic is “technology-independent”
- when we are done, we have to map to the technology
- “tech-mapping”