Tristate buffers

module tstate (EnA, EnB, BusA, BusB, BusOut); input EnA, EnB;

input [7:0] BusA, BusB;

output [7:0] BusOut;

assign BusOut = EnA ? BusA : 8’bZ;

assign BusOut = EnB ? BusB : 8’bZ;

endmodule

z is a tristated value