PPT Slide
always @(posedge clk) case (state) zero: begin out = 0; if (in) state = one1; else state = zero; end one1: if (in) begin
state = two1s;
out = 1;
end else begin
state = zero;
out = 0;
end two1s: if (in) begin
state = two1s;
out = 1;
end else begin
state = zero;
out = 0;
end
default: begin
state = zero;
out = 0;
end
endcase endmodule
Confusing: the output
logic is buried in the
state logic
…and compiler might give
you an extra register...
All outputs are registered
Previous slide
Next slide
Back to first slide
View graphic version