always example

module and_gate(out, in1, in2); input in1, in2; output out; reg out; always @(in1 or in2) begin

out = in1 & in2;

end

endmodule

Not a real register!!

Holds assignment in always block

specifies when block is executed i.e. triggered by changes in in1 or in2

The compiler will not use a register when it synthesizes this gate, because out changes whenever the inputs change. Can omit the module and write

wire out, in1, in2;

and (out, in1, in2);