Incomplete trigger or incomplete assignment

module and_gate (out, in1, in2); input in1, in2; output out; reg out; always @(in1) begin

out = in1 & in2;

end

endmodule

What if you omit an input trigger (e.g. in2)
- Compiler will insert a register to hold the state
  - Becomes a sequential circuit — NOT what you want

2 rules:

1) Include all inputs in the trigger list

2) Use complete assignments

? Every path must lead to an assignment for out

? Otherwise out needs a state element

What if you omit an input trigger (e.g. in2)