Verilog Continuous Assignment
assign C[15:0] = 4'h00ff;
assign #3 {Cout, S[3:0]} = A[3:0] + B[3:0] + Cin;
use of arithmetic operator
multiple assignment (concatenation)
delay of performing computation, only used by simulator, not synthesis
use of Boolean operators(~ for bit-wise, ! for logical negation)
bits can take on four values(0, 1, X, Z)
variables can be n-bits wide(MSB:LSB)
Assignment is continously evaluated
assign corresponds to a connection or a simple component with the described function
target is not a reg variable