Verilog Module

• Corresponds to a circuit component

  • “parameter list” is the list of external connections, aka “ports”
  • ports are declared “input”, “output” or “inout”
    • inout ports used on tri-state buses
  • port declarations declare the variables as wires

module full_addr (A, B, Cin, S, Cout); input A, B, Cin; output S, Cout;  assign {Cout, S} = A + B + Cin;endmodule

module name

inputs/outputs

ports

Previous slide

Next slide

Back to first slide

View graphic version