Verilog Numbers

• 14 - ordinary decimal number

• -14 - 2’s complement representation

• 12’b0000_0100_0110 - binary number with 12 bits (_ is ignored)

• 3’h046 - hexadecimal number with 12 bits

• Verilog values are unsigned

  • e.g. C[4:0] = A[3:0] + B[3:0];
  • if A = 0110 (6) and B = 1010(-6) C = 10000 not 00000i.e. B is zero-padded, not sign-extended

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