Verilog Data Types and Values
Bits - value on a wire
- 0, 1
- X - don’t care
- Z - undriven, tri-state
Vectors of bits
- A[3:0] - vector of 4 bits: A[3], A[2], A[1], A[0]
- Treated as an unsigned integer value
- Concatenating bits/vectors into a vector
- e.g. sign extend
- B[7:0] = {A[3], A[3], A[3], A[3], A[3:0]};
- B[7:0] = {3{A[3]}, A[3:0]};
- Style: Use a[7:0] = b[7:0] + c; Not: a = b + c; // need to look at declaration