Verilog/VHDL

• The “standard” languages

• Very similar

  • Many tools provide front-ends to both
  • Verilog is “simpler”
    • less syntax, fewer constructs
  • VHDL supports large, complex systems
    • better support for modularization
    • more grungy details
    • “hello world” is much bigger in VHDL

Previous slide

Next slide

Back to first slide

View graphic version