Design Problem #4 (due Wednesday, Jan 12)
Using the memory you designed in Problem #4, design a FIFO
- DataIn is added to the tail of the FIFO when Write is asserted (synchronous - happens on the CLK edge)
- The head of the FIFO is always available on DataOut
- the current head is removed when Read is asserted (synchronous - happens on the CLK edge)
- reset causes the FIFO to become empty (synchronous)
- Empty is 1 when the FIFO is empty, Full is 1 when the FIFO is full
- the N-1 hack for Full is fine
- You may use multiplexors, decoders, adders, counters, comparators, ...