Design Problem #3 (due Wednesday, Jan 12)

• Using registers, multiplexors and decoders, design a RAM with four entries

  • The ReadAddress indicates which entry is read to the DataOut
    • DataOut changes when the ReadAddress changes (asynchronous)
  • The WriteAddress indicates which entry is written from DataIn
  • The Write control signal indicates whether a write should be done
    • The write takes place on the CLK edge (synchronous)

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