Design Problem #5 (due Wednesday, Jan 19)

• Attach the FIFO we just designed to the RAM (described below)

  • Design a a controller that controls the FIFO and RAM to write the data in the FIFO to the RAM as fast as it can
  • Assume that the RAM Address is being generated by someone else
    • i.e. you can ignore it for now
  • The RAM writes the DataIn when Write is asserted (synchronously)
    • If it can’t do the write, it asserts Busy on the same clock tick
    • You must do the same Write again on the next cycle

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