Moore Verilog FSM (continued)
case (state) `zero: // last input was a zero
begin if (in) next_state = `one1; else next_state = `zero; end
`one1: // we've seen one 1 begin if (in) next_state = `two1s; else next_state = `zero; end
`two1s: // we've seen at least 2 ones begin if (in) next_state = `two1s; else next_state = `zero; end endcase
crucial to include all signals that are input to state and output equations
note that output only depends on state
always @(state) case (state) `zero: out = 0; `one1: out = 0; `two1s: out = 1; endcase