Mealy Verilog FSM
module reduce (CLK, reset, in, out); input CLK, reset, in; output out; reg out; reg state; // state variables reg next_state; always @(posedge CLK) if (reset) state = `zero; else state = next_state; always @(in or state) case (state) `zero: // last input was a zero begin out = 0; if (in) next_state = `one; else next_state = `zero; end `one: // we've seen one 1 if (in) begin next_state = `one; out = 1; end else begin next_state = `zero; out = 0; end endcase endmodule