Moore Verilog FSM
`define zero 2’b00 `define one1 2’b01 `define two1s 2’b10 module reduce (CLK, reset, in, out); input CLK, reset, in; output out; reg out; reg [1:0] state; // state variables reg [1:0] next_state; always @(posedge CLK) if (reset) state = `zero; else state = next_state;