Verilog BCD Counter Example

module BCDCount (CLK, clear, load, a0, a1); input CLK, reset, in; output a0, a1; reg a0, a1;

reg [1:0] state; // state variables reg [1:0] next_state;

 always @(posedge CLK) begin

state = next_state;

end

always @(state or clear or load) begin

case (state)

2’b00: next_state = 2’b01;

2’b01: next_state = 2’b10; 2’b10: next_state = 2’b11; 2’b11: next_state = 2’b00;

endcase if (clear) next_state = 2’b00;

… // handle load

end

assign a0 = state[0];

assign a0 = state[1];

endmodule

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