Verilog Implementation of a Counter (State Machine)

module Ctr (CLK, in, out); input CLK; input in; output out; reg out; // state variable reg [1:0] state; // local variable reg [1:0] next_state; always @(posedge CLK) // registers state = next_state;

always @(state or in) // Compute next_state[1:0] logic (D inputs) whenever state/inputs change. // Make sure state is always assigned to in every execution path!

// assign to the outputs

endmodule

• General view of a counter or state machine in verilog

Previous slide

Next slide

Back to first slide

View graphic version