PPT Slide

7 – Sequential Logic Examples

© 1996 Gaetano Borriello

Digital combination lock (PLD mapping)

55

E0900

+---------\ /---------+

| \ / |

| ----- |

clk | 1 40 | Vcc

| |

rst | 2 39 |

| |

value1 | 3 38 |

| |

ld1 | 4 37 |

| |

code1 | 5 36 |

| |

code2 | 6 35 |

| |

code3 | 7 34 | out

| |

code4 | 8 33 | mux3

| |

equal1 | 9 32 | mux2

| |

equal2 | 10 31 | mux1

| |

C1_1 | 11 30 | C3_4

| |

C1_2 | 12 29 | C3_3

| |

C1_3 | 13 28 | C3_2

| |

C1_4 | 14 27 | C3_1

| |

C2_1 | 15 26 | C2_4

| |

C2_2 | 16 25 | C2_3

| |

value2 | 17 24 |

| |

value3 | 18 23 | new

| |

value4 | 19 22 | ld2

| |

GND | 20 21 | ld3

| |

| |

`---------------------------'

• Entire data-path in one chip

• Including code registers

  • loaded from value inputs
  • keep ld1..ld3 secure

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