PPT Slide

7 – Sequential Logic Examples

© 1996 Gaetano Borriello

Section review

• Basic timing behavior of FSMs

  • when are inputs sampled, next state/outputs transition and stabilize
  • Moore and Mealy (sync and async) machine organizations
  • outputs = F(state) vs. outputs = F(state, inputs)

• FSM design

  • understanding the problem
  • generating state diagram
  • implementation using synthesis tools
  • iteration on design/specification to improve qualities of mapping
  • communicating state machines

• Four case studies

  • understand I/O behavior
  • draw diagrams
  • enumerate states for the "goal"
  • expand with error conditions
  • reuse states whenever possible

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