PPT Slide

7 – Sequential Logic Examples

© 1996 Gaetano Borriello

Digital combination lock (logic for new data-path)

54

P-Terms Fan-in Fan-out Type Name (attributes)

--------- ------ ------- ---- -----------------

2/6 6 1 Pin out.REG

1/1 1 1 Pin out.C

1/1 1 1 Pin out.SR

2/2 3 1 Node C1_1.REG

1/1 1 1 Node C1_1.C

2/2 3 1 Node C1_2.REG

1/1 1 1 Node C1_2.C

2/2 3 1 Node C1_3.REG

1/1 1 1 Node C1_3.C

2/2 3 1 Node C1_4.REG

1/1 1 1 Node C1_4.C

2/2 3 1 Node C2_1.REG

1/1 1 1 Node C2_1.C

2/2 3 1 Node C2_2.REG

1/1 1 1 Node C2_2.C

2/2 3 1 Node C2_3.REG

1/1 1 1 Node C2_3.C

2/2 3 1 Node C2_4.REG

1/1 1 1 Node C2_4.C

2/2 3 1 Node C3_1.REG

1/1 1 1 Node C3_1.C

2/2 3 1 Node C3_2.REG

1/1 1 1 Node C3_2.C

2/2 3 1 Node C3_3.REG

1/1 1 1 Node C3_3.C

2/2 3 1 Node C3_4.REG

1/1 1 1 Node C3_4.C

1/5 5 1 Node mux1.REG

1/1 1 1 Node mux1.SET

1/1 1 1 Node mux1.C

2/6 6 1 Node mux2.REG

1/1 1 1 Node mux2.CLR

1/1 1 1 Node mux2.C

2/6 6 1 Node mux3.REG

1/1 1 1 Node mux3.CLR

1/1 1 1 Node mux3.C

1/2 2 1 Node equal

3/8 6 1 Node code1

3/8 6 1 Node code2

3/8 6 1 Node code3

3/8 6 1 Node code4

4/4 4 1 Node equal1

4/4 4 1 Node equal2

=========

72/109 Best P-Term Total: 72

Total Pins: 11

Total Nodes: 22

Average P-Term/Output: 2

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