PPT Slide

7 – Sequential Logic Examples

© 1996 Gaetano Borriello

Digital combination lock (logic)

• ABEL output

• Design won't fit in any standard PLD

  • too many input signals
  • needs blocks with 44 product terms per output (inverted) for 4 signals
  • must try to break large functions into smaller ones (multi-level logic)

47

P-Terms Fan-in Fan-out Type Name (attributes)

--------- ------ ------- ---- -----------------

2/6 6 1 Pin out.REG

1/1 1 1 Pin out.C

1/1 1 1 Pin out.SR

1/1 1 1 Node mux1.SP

1/5 5 1 Node mux1.REG

1/1 1 1 Node mux1.C

2/6 6 1 Node mux2.REG

1/1 1 1 Node mux2.C

1/1 1 1 Node mux2.SR

2/6 6 1 Node mux3.REG

1/1 1 1 Node mux3.C

1/1 1 1 Node mux3.SR

1/4 4 1 Node equal

497/44 19 1 Node code1

497/44 19 1 Node code2

497/44 19 1 Node code3

497/44 19 1 Node code4

=========

2004/211 Best P-Term Total: 192

Total Pins: 20

Total Nodes: 8

Average P-Term/Output: 20

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