PPT Slide

7 – Sequential Logic Examples

© 1996 Gaetano Borriello

Digital combination lock (PLD implementation)

• Inputs

  • clk, rst, new
  • C1_1..C1_4, C2_1..C2_4, C3_1..C3_4
  • value1..value4

• Combinational outputs

  • equal

• Registered outputs

  • mux1..mux3
  • out

• Fitting

  • at least one block for each output – 5
  • equal will probably require 3 blocks (one per bit) plus 1 (for AND gate) – 4
  • needs 19 inputs and 1 output

46

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