PPT Slide

7 – Sequential Logic Examples

© 1996 Gaetano Borriello

Digital combination lock (introduce intermediate signals)

48

module lock2

interface (clk, rst, new, C1_1..C1_4, C2_1..C2_4, C3_1..C3_4, value1..value4 -> out);

title 'digital combination lock'

"Inputs

clk, rst, new pin;

C1_1..C1_4 pin;

C2_1..C2_4 pin;

C3_1..C3_4 pin;

value1..value4 pin;

"Outputs

out pin istype 'reg,buffer';

"Internal signals

mux1..mux3 node istype 'reg,buffer';

equal node;

code1..code4 node istype 'keep';

c

equal1,equal2 node istype 'keep';

"Alias for state register and encoding

SREG = [mux1..mux3,out];

S1 = [1,0,0,0];

S2 = [0,1,0,0];

S3 = [0,0,1,0];

ERR = [0,0,0,0];

OPEN = [0,0,0,1];

cntrl1 = [mux1, mux1, mux1, mux1];

ntrl2 = [mux2, mux2, mux2, mux2];

cntrl3 = [mux3, mux3, mux3, mux3];

EQUATIONS

SREG.clk = clk;

mux1.set = rst;

mux2.clr = rst;

mux3.clr = rst;

out.clr = rst;

[code1..code4] = ( (cntrl1 & [C1_1..C1_4])

# (cntrl2 & [C2_1..C2_4])

# (cntrl3 & [C3_1..C3_4]) );

equal1 = (code1 == value1) & (code2 == value2);

equal2 = (code3 == value3) & (code4 == value4);

equal = equal1 & equal2;

STATE_DIAGRAM SREG

state S1: if !new then S1

else if equal then S2 else ERR;

state S2: if !new then S2

else if equal then S3 else ERR;

state S3: if !new then S3

else if equal then OPEN else ERR;

state ERR: goto ERR;

state OPEN: goto OPEN;

END

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