PPT Slide

5 – Sequential Logic

© 1996 Gaetano Borriello

Typical timing specifications (cont'd)

• Transparent latch

  • setup and hold times
  • minimum clock width
  • propagation delays: high to low, low to high, maximum, typical
    • must consider both data-to-output and clock-to-output

26

measurements from falling clock edge or rising or falling data edge

CLK

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