PPT Slide

3 – Combinational Logic Implementation

© 1996 Gaetano Borriello

4

Two-level logic using NAND gates (cont'd)

• OR gate with inverted inputs is a NAND gate

  • de Morgan's: A' + B' = (A • B)'

• Two-level NAND-NAND network

  • inverted inputs are not counted
  • in a typical circuit, inversion is done once and signal distributed

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