Combinational logic implementation

3 – Combinational Logic Implementation

© 1996 Gaetano Borriello

• Two-level logic

  • implementations of two-level logic
  • NAND/NOR

• Multi-level logic

  • factored forms
  • and-or-invert gates

• Time behavior

  • gate delays
  • hazards

• Regular logic

  • multiplexors
  • decoders
  • PAL/PLAs
  • ROMs

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