// This module implements an 8-bit register with a synchronous reset
module reg8
  (input [7:0] D,
   input reset,
   input clock,
   output reg [7:0] Q
   );

   always @(posedge clock) begin
     if (reset) begin
       Q <= 8'b0000_0000;
     end else begin
       Q <= D;
     end
   end
   
endmodule