The first three solutions here are taken from the textbook resources.
There is a little sloppiness in some of the solutions, which will be
pointed out in red text.
I do not know what the "reset = 0" at the bottom of this
diagram means. It is typically taken for granted in FSM diagrams that if
reset is asserted, the machine will immediately transition back to the
reset state.
![](./sol1.png)
This FSM can be implemented with three states. S0 and S1
do exactly the same thing, and can be merged together.
![](./sol2.png)
This FSM is missing its reset state indicator. That's a
cardinal sin of FSM design. "Off" is the most natural state to mark as
the reset state.
![](./sol3.png)
- One possible solution
The code I used for grading