module fsmA(clk, rst, i, o); parameter st1 = 4'b0001; parameter st2 = 4'b0010; parameter st3 = 4'b0011; parameter st4 = 4'b0100; parameter st5 = 4'b0101; parameter st6 = 4'b0110; parameter st7 = 4'b0111; parameter st8 = 4'b1000; parameter st9 = 4'b1001; input clk, rst, i; output [1:0] o; reg [1:0] o; reg [3:0] state, nextState; always @ (posedge clk) begin if (rst) state <= st1; else state <= nextState; end always @ (i or state) begin o = 2'b00; case (state) st1: nextState = i ? st2 : st3; st2: nextState = i ? st6 : st4; st3: begin o = 2'b01; nextState = i ? st9 : st5; end st4: nextState = i ? st7 : st2; st5: begin o = 2'b10; nextState = i ? st7 : st5; end st6: begin o = 2'b10; nextState = i ? st8 : st1; end st7: begin o = 2'b11; nextState = i ? st8 : st4; end st8: nextState = i ? st6 : st8; st9: begin o = 2'b10; nextState = i ? st8 : st7; end endcase end endmodule module fsmB(clk, rst, i, o); parameter st1 = 4'b0001; parameter st2 = 4'b0010; parameter st3 = 4'b0100; parameter st4 = 4'b1000; input clk, rst; input [1:0] i; output o; reg o; reg [3:0] state, nextState; always @ (posedge clk) begin if (rst) state <= st1; else state <= nextState; end always @ (i or state) begin nextState = state; o = 1'b0; case (state) st1: begin if (i == 2'b00) nextState = st2; else if ((i == 2'b01) || (i == 2'b11)) nextState = st3; end st2: begin if (i == 2'b01) nextState = st3; else if (i == 2'b10) begin o = 1'b1; nextState = st1; end end st3: begin if (i == 2'b10) nextState = st4; else if ((i == 2'b00) || (i == 2'b11)) begin o = 1'b1; nextState = st2; end end st4: begin if (i == 2'b11) nextState = st1; else if ((i == 2'b01) || (i == 2'b10)) begin o = 1'b1; nextState = st2; end end endcase end endmodule