module testBenchExample();
  reg clk, rst, iA;
  reg [1:0] iB;
  wire [1:0] oA, oAs;
  wire oB, oBs;

  // instantiate the two state machines
  fsmA myA(clk, rst, iA, oA);
  fsmB myB(clk, rst, iB, oB);
  solutionfsmA smyA(clk, rst, iA, oAs);
  solutionfsmB smyB(clk, rst, iB, oBs);

  // generate a periodic clock signal
  always begin
    #10;
    clk = ~clk;
  end

  integer cnt, numErrs;
  reg [63:0] ins;


  initial begin
    // initialize clk, rst, iA and iB
    rst = 1;
    clk = 0;
    iA = 0;
    iB = 0;
    numErrs = 0;

    for (ins = 0; ins < 1024; ins = ins + 1) begin
      rst = 1;
      #100;
      rst = 0;
      for (cnt = 0; cnt < 16; cnt = cnt + 1) begin
        iA = ins[cnt]; iB = ins[(cnt * 2) +: 2];
/*        $display("Foo (ins=%d cnt=%d iA=%b iB=%b)", ins, cnt, iA, iB);*/
        #1;
        if ((oA == oAs) && (oB == oBs)) begin
        end
        else begin
          if (numErrs < 5) begin
            $display("Mismatch: Out A = %b vs %b  Out B = %b vs %b (ins=%d cnt=%d iA=%b iB=%b)", oA, oAs, oB, oBs, ins, cnt, iA, iB);
          end
          numErrs = numErrs + 1;
        end
        #19;
      end
    end
    $display("Number of errors: %d", numErrs);
    $finish;
  end

endmodule