HW1 Due April 17th - Solutions HW2 Due April 22nd Solutions HW3 Due May 1st Solutions HW4 Due May 15th Solutions HW5 Due May 24th Solutions HW6 Due May 31st Solutions HW7 Due June 7th Solutions
2013 Midterm Solutions
Past Midterms
Past Finals
May 31st : HW7 has been posted. There will be no labs next week.
May 23rd : HW6 has been posted.
May 23rd : Lab 7 instructions have been posted.
May 17th : Lab 6 instructions and HW5 have been posted.
May 11th : Lab 5 instructions have been posted.
May 8th : Midterm grades and solutions have been posted. Homework 4 has been posted, due in class on May 15th.
May 4th : Lab 4 instructions have been posted, and will resume next week.
April 27th : No Labs this week. A 1-hour slot at the beginning of each lab session will be dedicated for checking your Lab 3 deliverables.
April 25th : Class on Friday April 26th is cancelled. Midterm will be written in class on May 3rd.
April 24th : Homework 3 has been posted, due in class on May 1st.
April 20th : Lab 3 instructions have been posted.
April 14th: Due to the power outage and subsequent Active-HDL license server issues, the lab 1 deadline for the deliverables have been extended by a day. On friday after class, 30 mins will be dedicated to grading the final work for this lab. You are encouraged to get it done earlier to move on to lab 2 which will start this week. Homework 2 has been posted, due in class on April 22nd.
April 13th: Lab 2 instructions have been posted.
April 8th: Office hours have been posted: Thierry: Wed. 2:30-3:20pm in CSE216 Keith: Fri. 2:30-3:20pm in CSE216 Homework 1 has been posted, due in class on April 17th.
April 6th: Lab 1 has been posted - the lab sessions will start on the week of April 8th and will be graded on the week of April 15th.
Week of April 1st: Beginning of classes. No labs for this week.
Welcome to the Spring 2013 CSE 352 – Hardware Design and Implementation
Sorry for the late update! We finally geared up and got the website running. We hope that you had a great spring break and ready for this quarter.
The website contains essential (and useful) information for the class. Keep in mind that this document is not static, and that new information will be added over the entire quarter. Make sure to check the class e-mail archive frequently. Some links may be inactive until later in the quarter. If you have any problems with this document or the CSE 352 web, please send an email to the instructor and/or the TAs, or see us during office hours.
Instructor
Mark Oskin Email: oskin@cs.washington.edu Office Hours: By Appointment Office: CSE564
TAs
Thierry Moreau Email: moreau@cs.washington.edu Office Hours: Wed. 2:30-3:20pm Office: CSE216
Keith Miller Email: millerk@cs.washington.edu Office Hours: Fri. 2:30-3:20pm Office: CSE216
Staff
Raymond Zhang Email: rayz@cs.washington.edu
We will cover most of the concepts in Digital Design and Computer Architecture by Harris and Harris.
Digital Design and Computer Architecture
|
The text is available from Amazon. Errata reported to date can be found here.
| Mon | Tue | Wed | Thu | Fri |
|---|---|---|---|---|
| 3 Class Overview slides | 2 No lab | 3 MOSFETs, VLSI Read: chapter 1 | 2 No lab | 5 CMOS logic, gates |
| 8 Circuit delays, glitches Read: section 2.9, 3.5.3 HW1 Due April 17th | 3 Lab 1: Simple circuits I Lab1 intructions | 10 Latches and Flip-Flops Read: section 3.1, 3.2 | 3 Lab 1: Simple circuits I Lab1 intructions | 12 Synchronous Logic Design Read: section 3.3 |
| 15 No classes HW2 Due April 22nd | 16 Lab 2: Simple circuits II Lab2 intructions | 17 SRAM, DRAM Read: section 5.5 | 18 Lab 2: Simple circuits II Lab2 intructions | 19 Decoders Read: section 2.8 |
| 22 Adders Read: section 5.2.1 | 23 Lab 3: Intro to registers Lab3 intructions | 24 Carry-lookahead, multipliers HW3 Due May 1st | 25 Lab 3: Intro to registers Lab3 intructions | 27 No classes |
| 29 FPGAs Read: section 5.6.2 | 30 No Lab | 1 Verilog basics Read: Chapter 4 | 2 No Lab | 3 Midterm exam! |
| Mon | Tue | Wed | Thu | Fri |
|---|---|---|---|---|
| 6 FSMs Read: section 3.4 | 7 Lab 4: Designs in FPGAs Lab4 intructions | 8 Basic single cycle CPU - 1 Read: section 7.1-7.3 HW4 Due May 15th | 9 Lab 4: Designs in FPGAs Lab4 intructions | 10 Basic single cycle CPU - 2 slides |
| 13 Pipelining - 1 Read: section 7.5 | 14 Lab 5: Constructing the Y86 Processor I Lab5 intructions | 15 Pipelining - 2 | 16 Lab 5: Constructing the Y86 Processor I Lab5 intructions | 17 MIPS 5-stage pipeline HW5 Due May 24th |
| 20 Advanced topics: Branch prediction Read: section 7.8.2 Optional: Branch predictor | 21 Lab 6: Constructing the Y86 Processor II Lab6 intructions | 22 Advanced topics: Trace caches, Out of Order execution Read: section 7.8.4, 7.8.5 Optional: Pentium 4 Microarchitecture, OoO execution, Tomasulo's algorithm | 23 Lab 6: Constructing the Y86 Processor II Lab6 intructions | 24 Memory system: virtual address translation Read: section 8.4 HW6 Due May 31st |
| 27 Memorial Day | 28 Lab 7: Constructing the Y86 Processor III Lab7 intructions | 29 Multi-cores, cache coherence, memory consistency Optional: Cache coherence | 30 Lab 7: Constructing the Y86 Processor III Lab7 intructions | 31 Buses, I/Os Optional: High-Speed Layout Guidelines |
| Mon | Tue | Wed | Thu | Fri |
|---|---|---|---|---|
| 3 Memory-mapped I/Os, UART Read: section 8.5, 8.6 | 4 No lab | 5 Interrupts, DMA, BIOS | 6 No lab | 7 Exam review |
| 10 Final Exam! | 11 Finals Week | 12 Finals Week | 13 Finals Week | 14 Finals Week |
Course Goals
- Understanding digital logic at the gate and switch level including combinational and sequential logic elements
- Understanding clocking methodologies and system timing
- Learning how to specify digital-logic designs and compile these into digital circuit implementations
- Understanding the design and implementation of processor architectures
Course Syllabus
- Introduction to modern digital-logic design
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Combinational logic
- Switch logic and basic gates
- Boolean algebra
- Multilevel networks and transformations
- Programmable logic devices
- Delay and circuit performance
- Case studies
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Sequential logic
- Clocks and timing methodologies
- Registers, register files and memories
- Case studies
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Processor Design
- Arithmetic circuits
- Arithmetic and logic units
- Register and bus structures
- Instruction set implementation
- Memory system
- Pipelining
- Interrupts, memory-mapped I/O and embedded systems concepts
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Computer-aided design tools for logic design
- Schematic entry
- Hardware-description-languages
- Simulation and synthesis
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Practical topics
- Asynchronous inputs and metastability
- Serial and parallel communication
- Memories: RAM and ROM
- FPGA architectures
Workload
The course consists of the following components:
- Lectures: There will be about 30 lectures. Attendance and participation is expected at all of them.
- Laboratory Assignments: The lab assignments will be the focus of the course work and will be where you learn the CAD tools and put together your processor. Lab assignments are not canned. They are open-ended design sessions that will carry over from one week to the next and you will often need more time than the 3 hour lab session to complete your work. Attendance during the scheduled lab time when the TAs are available is very important. Please come to lab prepared so that you get as much done as possible with the extra help. Laboratory assignments will be closely tied to the written homework assignments and are intended to give you a taste of working with real digital hardware. Labs can be worked in pairs or individually.
- Assignments: Written homework with design problems will be assigned to reinforce class concepts. Many of these will mesh with the lab assignments and will require you to use the CAD design tools.
- Midterm exam: The midterm exam will test your knowledge on the first half of the course. The date, length and scope is being determined.
- Final exam: A two-hour exam during finals week as per the University’s final exam schedule.
We will try to ensure that the workload is typical for a four-credit course, namely, nine to twelve hours per week outside of the lectures. If we do not succeed, please let us know in whichever way you feel the most comfortable (person-to-person, e-mail, anonymous feedback) and explain which parts of the course are causing you to spend too much time non-productively.
We have structured the course so that spending an hour or two per day will maximize your efficiency. You will work this way in the real world—you cannot cram a three-month design assignment into the last night—so you may as well work this way now. Plus, you will understand the material better. If you leave the homework for the day before it is due you will not have time to ask questions when (not if) the software misbehaves.
Software tools frequently consume more time then they should. We have designed the assignments to get you up to speed gradually (over the period of a few weeks), but undoubtedly there will be some start-up cost (as with any new tool). Essentially, you are learning a new language, a compiler, and getting familiar with a process. Every tool imposes a certain model. Your frustration can be high until you assimilate that model and learn to use it effectively. Be sure to use the tutorials, and do not spend countless hours making no progress. Ask for help. Remember that these tools are written by engineers for engineers and will not necessarily conform to expectations you may have of consumer-oriented tools such as Word.
Assignments
Assignments are generally due a week after being posted, at the beginning of class on the assigned due date. Homework will no longer be accepted after a solution has been published (usually within 3-4 days). If you cannot hand in an assignment in time, please email the TAs before the assignment deadline to obtain an extension. You are strongly encouraged to review the assignment solutions to ensure you understood all the problems.
Your assignments must be neat and legible. We will not spend time trying to decipher messy work. We urge you to use the graphical and word processing tools that are readily available to you in all the labs in the department. Please make good use of the schematic diagram editor in the tools you'll be using to make neat circuit diagrams to include in your assignments.
Collaboration
Homework assignments: Unless specifically stated otherwise, we encourage collaboration on homework, provided (1) You spend at least 15 minutes on each and every problem alone, before discussing it with others, and (2) You write up each and every problem in your own writing, using your own words, and understand the solution fully. Copying someone else's homework is cheating (see below), as is copying the homework from another source (prior year's notes, etc.). Homework assignments are your chance to practice the concepts and make sure you know them well.
Labs: Unless specifically stated otherwise, the labs are meant to be conducted individually. Make sure you go through each step individually to understand the techniques and challenges behind digital systems design. The final labs on the microprocessor design will be conducted in groups.
Grading (may be revised)
Cheating
Cheating is a very serious offense. If you are caught cheating, you can expect a failing grade and initiation of a cheating case in the University system. Basically, cheating is an insult to the instructor, to the department and major program, and most importantly, to you and your fellow students. If you feel that you are having a problem with the material, or don't have time to finish an assignment, or have any number of other reasons to cheat, then talk with the instructor. Just don't cheat.
To avoid creating situations where copying can arise, never e-mail or post your solution files. You can post general questions about interpretation and tool use but limit your comments to these categories. If in doubt about what might constitute cheating, send the instructor email describing the situation.
Grade book is accessible here.
The Dropbox page is accessible here.
Labs
Chip Map Reference Lab1 Lab2 Lab3 Lab4 Lab5 Due Monday May 20th @ 11:59 pm - Lab6 Due Monday May 27th @ 11:59 pm - Lab7 Due Monday June 3rd @ 11:59 pm
Computers
We will be using the Dell PCs located in the Baxter Computer Engineering Laboratory, CSE 003. Please do not eat or drink in the laboratory, and respect both the equipment and your fellow students.
Logic Design Tools
We will be using Active-HDL from Aldec Inc. This tool combines schematics, the Verilog harware description language and simulation into one package. This tool will allow us to design at different levels of abstraction and interfaces to a variety of implementation tools for FPGAs and ASICs. We will be using the Aldec tools for CSE467 and CSE477, so learning it in CSE352 will be valuable for future classes.
Active-HDL from Aldec is installed in the Baxter Laboratory. We will be giving you tutorials for learning Active-HDL. These will be sufficient for this class, but you may want to check out the online documentation as well.
Remote Access
Active-HDL and Quartus are available outside of the 003 laboratory only for students currently enrolled in CSE352. It utilizes a license server on campus so your machine will require reasonable Internet access when you are using the tool. However, we have a limited number of concurrent licenses for this software. It is EXTREMELY IMPORTANT that if you use Active-HDL at home you completely shut down the applications when you are not actively using it so that the license is released for others to use. If you do not, and we have difficulty getting everyone access to the tool because of this, then we will have to limit home use.
If you understand this usage model and are willing to cooperate in making sure that the most students possible can make effective use of the tool, then you can find download instructions here.