Rashid Paper

From: Brian Milnes (brianmilnes_at_qwest.net)
Date: Wed Feb 11 2004 - 16:26:21 PST

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    Machine Independent Virtual Memory Management for Paged Uniprocessor and
    Multiprocessor Architectures - Rashid et al

    One of the Mach project's goals was to build a portable virtual memory
    management system for both uniprocessors and multiprocessors. Mach provided
    support for sparse address spaces, copy-on-write shared pages, memory mapped
    files and user space backing stores which can perform their own paging.

    The Mach virtual memory primitives allow the user to allocate/deallocate
    virtual memory, set its protection and inheritance and create memory objects
    that can be mapped into another process for communication. Mach represents
    this using a resident page table, an address map, memory objects and the
    hardware specific page map (pmap).

    The resident memory table is a linked list of boot time sized pages. The
    address mapping is a sorted doubly linked list and is optimized for
    allocation/deallocation, page faulting and protection changes. The memory
    objects are representations of contiguous blocks of memory which can be read
    or written and were reference count garbage collected. They have an
    associated pager process which is called via messages to pager ports.

     Memory sharing is implemented using shadow memory objects and memory
    sharing maps. When a new copy on write page is created, it gets a shadow
    memory object. When read write pages are shared they are managed using
    memory sharing maps which are split and merged as pages are remapped. The
    authors report that the most complex part of this is the handling of long
    chains of shared memory objects.

    The processor dependant memory management code is isolated in a single
    module, pmap.c. The module acts as a cache for virtual to physical memory
    translations for user processes as it can reconstruct this information from
    the architecture independent information. The ports of this were pretty
    cheap with only three weeks to boot it on each architecture.


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