Rashid et al. "Machine-Independent Virtual Memory Management for Paged Uniprocessor and Multiprocessor Architectures"

From: Cliff Schmidt (cliff_at_bea.com)
Date: Wed Feb 11 2004 - 14:45:04 PST

  • Next message: Richard Jackson: "Review: Rashid, et al. Machine-Independent Virtual Memory Management for Paged Uniprocessor and Multiprocessor Architectures."

    This paper describes the Mach operating system's memory management system.
    One of the key goals of the Mach system, even more so than the VAX/VMS
    system, was portability. At every level possible, a distinction is
    made between machine-independent code and machine-dependent code. In
    fact, the primary hardware requirement is the ability to handle and
    recover from page faults.

    The Mach Design section describes the basic abstractions, which didn't
    seem like anything new (although separating out threads from UNIX
    processes might have been new in 1987?). However, the indirection
    of message passing so that a thread can send a suspending message to
    another node on the network seemed like a new concept to me.

    The protection system includes an inheritance scheme that makes
    a UNIX fork much more efficient. Later on in the paper there are
    performance numbers that really show off this difference. Part
    of this performance data is also reflecting the shadowing system.
    The way shadowing is explained actually reminds me of something
    that I implemented for Phil Berstein's Transaction Processing
    class project. The idea of having one original copy and then
    several derived sets of changes to could be applied to it seemed
    similar, even though they were being used for somewhat different
    purposes. So the shadowing thing seems like a pretty useful
    construct; although, the authors also point out that garbage
    collection is required to keep the shadowing chains from getting
    out of control.

    I particularly found interesting the discussion of issues around
    differences between uniprocessors implementations and
    multiprocessors implementations. The cache consistency issues
    with TLBs in multiprocessor systems reminded me of the paper
    on performance issues with multithreaded, multiprocessors
    designs.


  • Next message: Richard Jackson: "Review: Rashid, et al. Machine-Independent Virtual Memory Management for Paged Uniprocessor and Multiprocessor Architectures."

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