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Week
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Topic
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Reading
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Homework Assignments
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1
3/30
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Architecture overview
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Let your eyes float over chapter 1. We won't cover this in class;
but it is good for your general background in computer architecture.
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Take the undergraduate exam; due April 6.
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Instruction set design
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Speedread chapter 2. This is a good summary of background instruction
set design material. Gaze at Appendix D. Gaze is a more cursory reading than speedread.
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2
4/6
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Instruction-level parallelism
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Read section 3.1.
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Read the project report guidelines and the sample project report.
Experiments with branch techniques; due April 20.
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Basics of pipelining
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Sections A.1 - A.2 is a review of the basics of pipelining and
could replace reading in the undergraduate text. Only read it if you need
it.
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Dynamic branch prediction
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Read sections 3.4 and 3.5, pp. A-24-A-26, and Fig. 3-40 p. 249.
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Predicated execution
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pp. 340-344, 356, 358.
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Exceptions & pipelining
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Read A-37 to A-45 and A-54 to A-56.
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3
4/13
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Superscalars & static scheduling
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Read pp. 215-220.
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Overview of dynamic scheduling
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Read pp. 181-184, 220-224.
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Tomasulo's algorithm
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Read pp. 184-196.
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4
4/20
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R10000-style dynamic scheduling (a physical register pool)
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The Smith/Sohi article on
superscalars.
The R10000 article. Read from Register
mapping, p. 32 through Register files, p. 35.
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Evaluation of in-order versus out-of-order implementations.
Due May 4.
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Pentium-style dynamic scheduling (reorder buffers)
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Read pp. sections 3.7, 3.10 and 3.13. I've included two articles on the Pentium Pro
(ps , pdf) and (ps , pdf) . It's only necessary
to read the sections on the pipeline and dynamic scheduling at this point.
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5
4/27
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Software techniques to exploit ILP
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Pp. 304-314 cover 2 techniques that we have already discussed. If you
want our authors' take on them, this is the place to read. Pp. 329-340 cover
compiler techiques that we will discuss briefly.
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VLIW machines
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Read pp. 315-319.
Read section 4.7 and the IA-64 papers. In the HP/Intel
architecture
paper omit the memory model, software pipelining, & floating point. In
the
Intel implementation paper, omit floating point
again, IA-432 compatibility & machine resources per port. In the MPR paper, read only the first 4 pages. There is also a
critique by a rival .
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Hardware support for compiler speculation
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Read pp. 345-351.
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Wrap-up
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Read section 4.10.
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6
5/4
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Basics of caches
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Read pp. 390-410, 423-430.
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Cache evaluation. Due May 11.
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Advanced caching techniques
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Read pp. 410-413, section 5.4, pp. 430-435, sections 5.6, 5.7.
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Main memory
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Read sections 5.8, 5.9.
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7
5/11
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Tera-style multithreading
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Read the Tera paper (PS, PDF).
Tera's runtime system (not required - this is just in
case the OS/RT students are interested).
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Cache coherency protocol design & evaluation. Due June 1.
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Simultaneous multithreading
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Read section 6.9 and the SMT paper
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8
5/18
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Overview of multiprocessing
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Read section 6.1.
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Cache coherence, snooping and directory protocols
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Read sections 6.3 - 6.6.
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Synchronization
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Read section 6.7.
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9
5/25
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Content and date of the final.
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Dataflow machines and WaveScalar.
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Read about the Manchester dataflow machine for an
overview of dataflow machines in general and the "case for"
WaveScalar paper ; the other WaveScalar papers on the
RTL-level implementation and support for multiple
threads are optional.
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Course evaluations.
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10
6/1
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Current architecture research at UW CSE: guest speakers.
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Andrew Petersen, UW graduate student, on Quantum Computing.
Brian Van Essen, UW graduate student, on FPGAs
Margaret Martonosi, professor on sabbatical from Princeton, on ZebraNet. Read the ZebraNet hardware
experiences paper; the software experiences paper is optional.
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6/8
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Final from 7pm to 9pm in EE1-045. Douglas will proctor the exam.
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