Example on how to reserve the WB stage

Time in ID stage Operation Shift register

t multd 000 000 001

t +1 int 001 000 010

t + 2 int 011 000 100

t + 3 addd 110 00X 000

Note: multd and addd want WB at time t + 9. addd will be asked to stall one cycle

Instructions complete out of order (e.g., the two int terminate before the multd)