Conflict in using the WB stage
Several instructions might want to use the WB stage at the same time
- E.g.,A Multd issued at time t and an addd issued at time t + 3
Solution: reserve the WB stage at ID stage (scheme already used in CRAY-1)
- keep track of WB stage usage in shift register
- reserve the right slot. If busy, stall for a cycle and repeat
- shift every clock cycle