Multiple cycle impl. (cont’d)
3. ALU execution (Part I)
ALUoutput <- A op B (if Arit-logic)
ALUoutput <- A + sign-extend (IR[15:0])
for immediate or memory address computation
If (A = B) then PC <- target else PC <- NPC
For branches; of course can be other conditions
4. Memory access or ALU execution (Part II)
Memory-data <- Memory[ALUoutput] (Load)
Memory[ALUoutput] <- B (Store)
Reg[IR[15:11]] <- ALUoutput (if Arit-logic)
Reg[IR[20:16]] <- Memory-data