Multiple cycle implementation (RTL level)

• For example (using MIPS R3000 ISA):

1. Instruction fetch and increment PC

IR <- Mem[PC]

NPC <- PC + 4

2. Instruction decode and register read

A <- Reg[IR[25:21]] (1st input to ALU)

B <- Reg[IR[20:16]] (2nd input to ALU)

target <- NPC + sign-extend(IR[15:0]*4) (in case the

instruction is a branch)

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