Cache Coherency -- The Problem

• Independent processors modifying shared locations can change values without other processors being aware of it

P1

a: 4 5

P2

a: 5

P3

a: 4

a: 4 5 Memory

P1 reads a into cache

P3 reads a into cache

P1 writes a to 5, and

writes through to main

memory, correcting it

-- P3 has stale data --

P2 reads a into cache

Memory is arbiter of

present value ... move

it closer to processors

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