CSE 548: Computer Architecture

Winter 1999

Instructor
Susan Eggers (eggers@cs.washington.edu)
Office: 315 Sieg. 543-2118
Office Hours: Tuesday 11:30 - 12:20 and Friday 1:30 - 2:20
TA
Sujay Parekh (sparekh@cs.washington.edu)
Office: 109A Chateau. 616-1846
Office Hours: Monday 11:30 - 12:20, or by appointment

Handouts

  1. Course Overview
  2. Schedule
  3. HW 1
  4. HW 2
  5. HW 3
  6. HW 4
  7. HW 5

Check outside Susan's door for other handouts taken from journals and publications.

Slides

  1. Overview
  2. Instruction Set Design
  3. Pipelining I - Basics
  4. Pipelining II - Dynamic Branch Prediction
  5. Pipelining III - Complications
  6. ILP
  7. Dynamic scheduling
  8. Superscalars
  9. Processor pipeline comparisons
  10. Memory system I - Basics
  11. Memory system II- Optimizations
  12. Memory system III - Physical and Virtual memory
  13. I/O sub-system
  14. Multiprocessors
  15. Synchronization
  16. Memory Consistency Models
  17. Final

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