Retro school children University of Washington Computer Science & Engineering
 CSE 548: Computer Architecture - Winter 2006
  CSE Home   About Us    Search    Contact Info 

 Course Home
   

CSE 548 Schedule (Winter 2006)

This course schedule will be updated, so check it often.
The dates for the readings indicate the day that the reading should have been read.

 
Class
Topic
Reading
Project Milestones
ISA
1/4 & 1/9
Architecture overview Let your eyes float over chapter 1. We won't cover this in class; but it is good for your general background in computer architecture. Start thinking about your project topic and pick a project partner.
Instruction set design Speedread chapter 2. This is a good summary of background instruction set design material. Gaze at Appendix D. Gaze is a more cursory reading than speedread.
Dataflow Computers
1/11, 1/18, 1/23
Dataflow machines.
After looking them over, I don't like any of the papers on the early dataflow machines. Just listen to the lecture. If you want additional reading after the lecture, I can point you to papers on individual topics. But there is no general overview. Application (for WaveScalar) or design topic (Von Neumann) should hopefully be chosen before January 18. WaveScalar teams can check with Andrew Petersen, who will be giving the 1/18 lecture. The other projects can send email to Andrew Putnam and me. Our back-up is 1/23, when Putnam and I will both be back in town.
WaveScalar assembly The WaveScalar Architecture.
WaveScalar architecture and implementation. An overview of the WaveScalar implementation.
Pipelining
1/25, 1/30
Instruction-level parallelism Read section 3.1.
Basics of pipelining Sections A.1 - A.2 is a review of the basics of pipelining and could replace reading in the undergraduate text. Only read it if you need it.
Dynamic branch prediction Read sections 3.4 and 3.5, pp. A-24-A-26, and Fig. 3-40 p. 249.
Predicated execution pp. 340-344, 356, 358.
Exceptions & pipelining Read A-37 to A-45 and A-54 to A-56.
Execution cores
2/1, 2/6, 2/8
Superscalars & static scheduling Read pp. 215-220. Baseline experiments should be done February 1. Keep in touch; let us know how you're coming along -- it's a long time until the next due date. Turn in a report based on the First Milestone Guidelines before class on Wednesday.
Overview of dynamic scheduling Read pp. 181-184, 220-224.
Tomasulo's algorithm Read pp. 184-196.
R10000-style dynamic scheduling (a physical register pool) The Smith/Sohi article on superscalars.
The R10000 article. Read from Register mapping, p. 32 through Register files, p. 35.
Pentium-style dynamic scheduling (reorder buffers)
Read pp. sections 3.7, 3.10 and 3.13. I've included two articles on the Pentium Pro here , and here . It's only necessary to read the sections on the pipeline and dynamic scheduling at this point.
VLIW
2/13, 2/15
Software techniques to exploit ILP
Pp. 304-314 cover 2 techniques that we have already discussed. If you want our authors' take on them, this is the place to read. Pp. 329-340 cover compiler techiques that we will discuss briefly.
Milestone 2 due in class on February 15 .

Have your application's hotspot(s) written in WaveScalar assembly and simulated on the simulators. Turn in is an e-mail message describing what you've done, and your commented assembly code.
VLIW machines Read pp. 315-319.
Read section 4.7 and the IA-64 papers. In the HP/Intel architecture paper omit the memory model, software pipelining, & floating point. In the Intel implementation paper, omit floating point again, IA-32 compatibility & machine resources per port. In the MPR paper, read only the first 4 pages. There is also a critique by a rival .
Hardware support for compiler speculation
Read pp. 345-351.
Wrap-up
Read section 4.10.
Memory Hierarchy
2/22
Basics of caches This is standard undergraduate material. You might skip the reading and just look at the slides for a review. Only read pp. 390-410, 423-430 if the slides seem incomprehensible.
Advanced caching techniques Read pp. 410-413, section 5.4, pp. 430-435, sections 5.6, 5.7.
Main memory Read sections 5.8, 5.9.
Multithreading
2/27, 3/1
Tera-style multithreading Read the Tera paper.
Simultaneous multithreading Read section 6.9 and the SMT paper .
Multiprocessors
3/6, 3/8
Overview of multiprocessing Read section 6.1.
Cache coherence, snooping and directory protocols Read sections 6.3 - 6.6.
Synchronization Read section 6.7.
Quantum Computing
3/13
Guest Lecturer
David Bacon
The Scientific American article will provide an overview of the technology. This UW research paper discusses a particular quantum architecture. These papers are optional reading, but I thought you might enjoy them.
March 13: Project reports due at the start of class.)
Optimize your assembly in some way and analyze stats to explain the resulting execution. Turn in a report in the form described in the handout, plus your commented assembly code. Optimizations after the first are extra credit.



CSE logo Computer Science & Engineering
University of Washington
Box 352350
Seattle, WA  98195-2350
(206) 543-1695 voice, (206) 543-2969 FAX
[comments to aputnam]