Simple ALU (top level)

module alusim(a,b,Carryin,Result,Overflow,Operation);

input a,b,Carryin;

output Result,Overflow;

input Operation;

wire t0, t1,t2;

and g0(t0,a,b);

fullAdd1 g1( t2, t1, Overflow, a, b, Carryin);

mux2 g2(Result,Operation,t0,t1);

endmodule

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