Technology Mapping for LUT FPGAs

• Make sure all nodes in graph have at most k inputs

  • Factor nodes that have too many inputs
    • Decomposition
    • Factoring
  • Collapse nodes that have too few inputs (if you can)

• Synthesis process typically ends up with nodes with small support

  • Factor large nodes first
  • Then collapse small nodes

• Lots of ongoing research on how to do this well

Previous slide

Back to first slide

View graphic version