Restructuring Multi-Level Logic for Speed
A is a late arriving input that is moved closer to the output by restructuring the logic (i.e., changing DAG structure)
Decrease fanout of nodes
- more destinations for a signal implies slower transmission
- elimination, duplication
Decrease fanin of nodes
- gate speed proportional to square of number of inputs (1st order)
- decomposition, simplification
Move late input closer to outputs
- make path to output shorter, pre-compute other logic
- Shannon decomposition (f = a fa + a’ fa’)