What you will do...

• Use a synthesizeable subset of Verilog

  • e.g. no “initial” blocks
  • Using structural and “synthesizeable” behavioral Verilog

• Will not simulate your Verilog code

  • You can experiment using the Veriwell simulator

• Will synthesize your code

  • FPGA Express (Synopsis) is built into the tools

• Will simulate your netlist

  • After synthesis
  • All your code will synthesize (by necessity)

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