CSE 467: Advanced Digital Design

Winter 2015

Teaching Staff

Mark Oskin
Office: CSE564
Email: oskin@cs.washington.edu
Office Hours: TBD

Teaching Assistants:
Vincent Lee
Email: vlee2@cs.washington.edu
Office Hours: Monday 2:30-3:30PM

Mark Wyse
Email: wysem@cs.washington.edu
Office Hours: Monday 3:30-4:30PM

Unless otherwise stated, all office hours will be held in CSE003 (the lab).

Lecture and Lab

Lecture: WF 12:30PM-1:50PM
Location: EEB031

Lab: Th 2:30PM-5:20PM
Location: CSE003

Project Specifications

Project specifications for each phase will be posted here in addition to the course mailing list.

Project Phase 0: Course Introduction and Graphics Pipeline Software Model [PDF]
Due Tuesday January 13th @ 11:59PM

Project Phase 1: Introducing the GPU Instruction Set [PDF]
Code Due Sunday January 25th @ 11:59PM
Demo Due Monday January 26th

Project Phase 2: Building the Framebuffer, Z-Buffer, and Display Interface [PDF]
Design Document Due Saturday January 24th @ 11:59PM
Design Review Due Monday January 26th
Code Due Tuesday February 3rd @ 11:59PM
Demo Due Thursday February 5th

Project Phase 3: Building the Graphics Processing Unit [PDF]
Design Document Due Saturday February 7th @ 11:59PM
Design Reviews Monday February 9th 2:30PM-5:30PM
Due Tuesday February 24th @ 11:59PM

Project Phase 4: Build the GPU Warps and Implementing Warp Scheduling

Final Project Demostrations
Final Demonstrations in Lab (CSE003)
Thursday March 20th 12:00PM-1:30PM

Project Resources

  • Altera DE1 SoC User Manual [PDF]
  • Altera DE1 SoC Getting Started Guide [PDF]
  • CSE467 Assembler, Debugger, and Disassembler [Link]
  • PGM Example Code [Link]
  • Your Favorite teapot.off File [Link]
  • Introduction to Quartus II Software [Link]
  • Quartus II Handbook [Link]
  • Quartus II Base Project Archive [Link]
  • HPS Bidirectional FIFO Link Example [Link]
  • SDRAM Controller Example [Link]
  • Course Description

    CSE 467 Advanced Digital Design (4): Advanced techniques in the design of digital systems. Hardware description languages, combinational and sequential logic synthesis and optimization methods, partitioning, mapping to regular structures. Emphasis on reconfigurable logic as an implementation medium. Memory system design. Digital communication including serial/parallel and synchronous/asynchronous methods. Prerequisite: either CSE 352 or CSE 370; either CSE 326 or CSE 332.

    Course Goals

    To provide in-depth understanding of digital systems and their design, from specification and simulation to construction and debugging. Students should learn how to build and optimize algorithms to run very quickly on custom hardware.


    There is no homework, midterm, or final for this class. The project will compose the entire grade for this course. More specifically: Homework (0%), Midterm (0%), Final(0%), Project(100%).

    Most of this website is borrowed from the 2013 Winter offering of CSE467 (Thanks Gabe Cohn)
    The CSE 467 Website: Copyright 2013, Department of Computer Science & Engineering, University of Washington.