CSE 467

Logic Design Tools

We will be using Active-HDL from Aldec Inc. This tool combines schematics, the Verilog harware description language and simulation into one package. This tool will allow us to design at different levels of abstraction and interfaces to a variety of implementation tools for FPGAs and ASICs.
Version 6.2 of Aldec is installed in the Baxter Laboratory. We will be giving you tutorials for learning Active-HDL. These will be sufficient for this class, but you may want to check out the online documentation as well.

Several tutorials are available:

Active-HDL Tutorial 1 Creating and Simulating Simple Schematics (pdf version)

Active-HDL Tutorial 2 Hierarchical Designs and Test Fixtures (pdf version)

Active-HDL Tutorial 3 Introduction to Using Verilog in Active-HDL (pdf version)

Active-HDL PAL Tutorial Using Active-HDL to Compile to PALs (pdf version)

Interactive Aldec tutorial (on all lab computers) zip file

Lab Equipment

Oscilloscope tutorial

Logic analyzer tutorial (pdf)

Comments to: cse467-webmaster@cs.washington.edu